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seiko epson corporation 1 pf494-08 E0C6235 4-bit single chip microcomputer low voltage operation products l core cpu architecture l programmable svd circuit l event counter/sound generator n description the E0C6235 is an advanced single-chip cmos 4-bit microcomputer consisting of the e0c6200 cmos 4-bit core cpu. it also contains the rom, ram, lcd driver, event counter with dial input feature, programmable svd circuit, stopwatch counter and time base counter. with wide operating voltage range and low power consump- tion, the E0C6235 provides an excellent solution for the low-power consumption systems with manganese dry cell. n features l cmos lsi 4-bit parallel processing l clock ..................................................... 32.768khz/38.400khz/500khz (typ.) l instruction set ........................................ 108 instructions l instruction cycle time ............................ 153sec, 214sec or 366sec at 32khz 130sec, 182sec or 313sec at 38.4khz 10sec, 14sec or 24sec at 500khz (depending on instruction) l rom capacity ....................................... 4,096 12 bits l ram capacity ........................................ 576 4 bits (lcd segment memory jointly used) l input port ............................................... 9 bits (pull-down resistors are available by mask option) l output port ............................................ 8 bits (clock output or buzzer output is available by mask option) l i/o port .................................................. 8 bits (pull-down resistors are available by mask option) l serial i/o port ........................................ 1 port (clock sync.) l event counter ........................................ 8 bits (dial input function) l lcd driver ............................................. 48 segments 3 commons/48 segments 4 commons (1/3 or 1/4 duty is selectable by mask option) l built-in lcd power circuit ..................... voltage regulator circuit; doubler or tripler l built-in svd circuit ................................ 1.2v fixed (e0c62l35) 1.05 to 1.40v programmable (e0c62l35) 2.20 to 2.55v programmable (E0C6235/62a35) l built-in amp .......................................... operational amp for mos input analog comparator l built-in watchdog timer l built-in time base counter ..................... 2 lines l interrupts ............................................... external : input interrupt 3 lines internal : timer interrupt 1 line serial i/o interrupt 1 line stopwatch interrupt 1 line l built-in sound generator ........................ with digital envelope (8 sounds programmable) l current consumption ............................ e0c62l35 halt mode (32khz) : 1.5a (typ.) E0C6235 halt mode (32khz) : 1.8a (typ.) e0c62a35 halt mode (32khz) : 2.0a (typ.) operating mode (500khz) : 130a (typ.) l package ................................................ qfp5-100pin (plastic), qfp15-100pin (plastic) die form n line up model e0c62l35 E0C6235 e0c62a35 supply voltage 1.5v (0.9v to 1.7v) 3.0v (1.8v to 3.5v) 3.0v (2.2v to 3.5v) clock 32khz or 38.4khz (crystal oscillation) 32khz or 38.4khz (crystal oscillation) 32khz or 38.4khz (crystal oscillation) & 500khz (ceramic or cr oscillation) twin clocks can be used in e0c62a35.
2 E0C6235 n block diagram n pin configuration 51 80 31 50 index 30 1 100 81 E0C6235 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 com1 com0 seg47 seg46 seg45 seg44 seg43 seg42 seg41 seg40 seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 no. pin name 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 seg24 test seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 no. pin name 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 seg0 ampp ampm k23 k22 k21 k20 k10 k03 k02 k01 k00 sin sout n.c. sclk p03 p02 p01 p00 n.c. n.c. p13 p12 p11 n.c. = no connection no. pin name 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 p10 r03 r02 r01 r00 r12 r11 r10 r13 v ss reset osc4 osc3 v s1 osc2 osc1 v dd v l3 v l2 v l1 ca cb cc com3 com2 no. pin name com0~3 v k00~03, k10, k20~23 p00~03, p10~13 r00~03, r10~13 sin sclk dd osc4 osc3 osc2 osc1 rese t seg0~47 test v l1~3 ca~cc v s1 v ss sout power controller lcd driver ram 576 words x 4 bits rom 4,096 words x 12 bits osc system reset control ampp ampm sound generator event counter svd interrupt generator input port i/o port output port serial interface timer stop watch comparator core cpu e0c6200 qfp5-100pin
3 E0C6235 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 seg47 seg46 seg45 seg44 seg43 seg42 seg41 seg40 seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 test no. pin name 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 n.c. seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 no. pin name 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 ampp ampm k23 k22 k21 k20 k10 k03 k02 k01 k00 sin sout n.c. sclk n.c. p03 p02 p01 p00 p13 p12 p11 p10 r03 n.c. = no connection no. pin name 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 r02 r01 r00 r12 r11 r10 r13 v ss reset osc4 osc3 v s1 osc2 osc1 v dd v l3 v l2 v l1 ca cb cc com3 com2 com1 com0 no. pin name 51 75 26 50 index 25 1 100 76 E0C6235 qfp15-100pin n pin description v dd v ss v s1 v l1 v l2 v l3 ca?c osc1 osc2 osc3 osc4 k00?03, k10 k20?23 p00?03 p10?13 r00?03 r10 r13 r11 r12 sin sout sclk ampp ampm seg0?7 com0? reset test pin name i i o o o o i o i o i i/o o o o o o i o i/o i i o o i i in/out power source (+) terminal power source (-) terminal oscillation and internal logic system regulated voltage output terminal lcd system regulated voltage output terminal (approx. -1.05 v) lcd system booster output terminal (v l1 x 2) lcd system booster output terminal (v l1 x 3) booster capacitor connecting terminal crystal oscillation input terminal crystal oscillation output terminal ceramic or cr oscillation input terminal (switchable by mask option, 62a35 only) ceramic or cr oscillation output terminal (switchable by mask option, 62a35 only) input terminal i/o terminal output terminal output terminal (dc or bz output may be selected by mask option) output terminal (dc or bz output may be selected by mask option) output terminal (dc or siof output may be selected by mask option) output terminal (dc or fout output may be selected by mask option) serial interface input terminal serial interface output terminal serial interface clock input/output terminal analog comparator non-inverted input terminal analog comparator inverted input terminal lcd segment output terminal (convertible to dc output by mask option) lcd common output terminal initial reset input terminal test input terminal qfp5-100 92 85 89 95 94 93 96?8 91 90 88 87 54?2 67?0 73?6 77?0 83 84 82 81 63 64 66 52 53 3?6, 28?1 1, 2, 99, 100 86 27 qfp15-100 90 83 87 93 92 91 94?6 89 88 86 85 53?1 67?4 75?8 81 82 80 79 62 63 65 51 52 1?4, 26?0 97?00 84 25 pin no. function
4 E0C6235 n electrical characteristics l absolute maximum ratings E0C6235/62a35 rating supply voltage input voltage (1) input voltage (2) permissible total output current * 1 operating temperature storage temperature soldering temperature / time permissible dissipation * 2 * 1: * 2: the permissible total output current is the sum total of the current (average current) that simultaneously flows from the outpu t pins (or is draw in). in case of plastic package (qfp5-100pin, qfp15-100pin). symbol v ss v i v iosc s i vss topr tstg tsol p d value -5.0 to 0.5 v ss - 0.3 to 0.5 v s1 - 0.3 to 0.5 10 -20 to 70 -65 to 150 260 c, 10sec (lead section) 250 unit v v v ma c c mw (v dd =0v) e0c62l35 rating supply voltage input voltage (1) input voltage (2) permissible total output current * 1 operating temperature storage temperature soldering temperature / time permissible dissipation * 2 * 1: * 2: the permissible total output current is the sum total of the current (average current) that simultaneously flows from the outpu t pins (or is draw in). in case of plastic package (qfp5-100pin, qfp15-100pin). symbol v ss v i v iosc s i vss topr tstg tsol p d value -2.0 to 0.5 v ss - 0.3 to 0.5 v s1 - 0.3 to 0.5 10 -20 to 70 -65 to 150 260 c, 10sec (lead section) 250 unit v v v ma c c mw (v dd =0v) l recommended operating conditions E0C6235 condition supply voltage oscillation frequency symbol v ss f osc1 remark v dd =0v either one is selected unit v khz khz (ta=-20 to 70 c) max. -1.8 typ. -3.0 32.768 38.400 min. -3.5 e0c62l35 condition supply voltage oscillation frequency * 1: * 2: when switching to heavy load protection mode. the possibility of lcd panel display differs depending on the characteristics of the lcd panel. symbol v ss f osc1 remark v dd =0v v dd =0v, with software control * 1 v dd =0v, when the analog comparator is used either one is selected unit v v v khz khz (ta=-20 to 70 c) max. -1.1 -0.9 * 2 -1.2 typ. -1.5 -1.5 -1.5 32.768 38.400 min. -1.7 -1.7 -1.7 e0c62a35 condition supply voltage oscillation frequency (1) oscillation frequency (2) symbol v ss f osc1 f osc3 remark v dd =0v either one is selected duty 50 5% unit v khz khz khz (ta=-20 to 70 c) max. -2.2 600 typ. -3.0 32.768 38.400 500 min. -3.5 50
5 E0C6235 l dc characteristics E0C6235/62a35 unit v v v v a a a a ma ma ma ma a a a a a a (unless otherwise specified: v dd =0v, v ss =-3.0v, f osc1 =32.768khz, ta=25 c, v s1 /v l1 ? l3 are internal voltage , c1?6=0.1 f) max. 0 0 0.8? ss 0.9? ss 0.5 16 100 0 -1.8 -0.9 -3 -3 -200 typ. min. 0.2? ss 0.1? ss v ss v ss 0 4 25 -0.5 6.0 3.0 3 3 200 characteristic high level input voltage (1) high level input voltage (2) low level input voltage (1) low level input voltage (2) high level input current (1) high level input current (2) high level input current (3) low level input current high level output current (1) high level output current (2) low level output current (1) low level output current (2) common output current segment output current (during lcd output) segment output current (during dc output) symbol v ih1 v ih2 v il1 v il2 i ih1 i ih2 i ih3 i il i oh1 i oh2 i ol1 i ol2 i oh3 i ol3 i oh4 i ol4 i oh5 i ol5 v ih1 =0v no pull down resistor v ih2 =0v with pull down resistor v ih3 =0v with pull down resistor v il =v ss v oh1 =0.1? ss v oh2 =0.1? ss v ol1 =0.9? ss v ol2 =0.9? ss v oh3 =-0.05v v ol3 =v l3 +0.05v v oh4 =-0.05v v ol4 =v l3 +0.05v v oh5 =0.1? ss v ol5 =0.9? ss condition k00?3, k10, k20?3 p00?3, p10?3, sin sclk, reset, test k00?3, k10, k20?3 p00?3, p10?3, sin sclk, reset, test k00?3, k10, k20?3 p00?3, p10?3, sin, sclk ampp, ampm, reset k00?3, k10, k20?3 sin, sclk p00?3, p10?3 reset, test k00?3, k10, k20?3 p00?3, p10?3, sin, sclk ampp, ampm, reset , test r10, r11, r13 r00?3, r12, p00?3, p10?3 sout, sclk r10, r11, r13 r00?3, r12, p00?3, p10?3 sout, sclk com0?om3 seg0?eg47 seg0?eg47 e0c62l35 unit v v v v a a a a a a a a a a a a a a (unless otherwise specified: v dd =0v, v ss =-1.5v, f osc1 =32.768khz, ta=25 c, v s1 /v l1 ? l3 are internal voltage , c1?6=0.1 f) max. 0 0 0.8? ss 0.9? ss 0.5 10 60 0 -300 -150 -3 -3 -100 typ. min. 0.2? ss 0.1? ss v ss v ss 0 2 12 -0.5 1,400 700 3 3 100 characteristic high level input voltage (1) high level input voltage (2) low level input voltage (1) low level input voltage (2) high level input current (1) high level input current (2) high level input current (3) low level input current high level output current (1) high level output current (2) low level output current (1) low level output current (2) common output current segment output current (during lcd output) segment output current (during dc output) symbol v ih1 v ih2 v il1 v il2 i ih1 i ih2 i ih3 i il i oh1 i oh2 i ol1 i ol2 i oh3 i ol3 i oh4 i ol4 i oh5 i ol5 v ih1 =0v no pull down resistor v ih2 =0v with pull down resistor v ih3 =0v with pull down resistor v il =v ss v oh1 =0.1? ss v oh2 =0.1? ss v ol1 =0.9? ss v ol2 =0.9? ss v oh3 =-0.05v v ol3 =v l3 +0.05v v oh4 =-0.05v v ol4 =v l3 +0.05v v oh5 =0.1? ss v ol5 =0.9? ss condition k00?3, k10, k20?3 p00?3, p10?3, sin sclk, reset, test k00?3, k10, k20?3 p00?3, p10?3, sin sclk, reset, test k00?3, k10, k20?3 p00?3, p10?3, sin, sclk ampp, ampm, reset k00?3, k10, k20?3 sin, sclk p00?3, p10?3 reset, test k00?3, k10, k20?3 p00?3, p10?3, sin, sclk ampp, ampm, reset , test r10, r11, r13 r00?3, r12, p00?3, p10?3 sout, sclk r10, r11, r13 r00?3, r12, p00?3, p10?3 sout, sclk com0?om3 seg0?eg47 seg0?eg47
6 E0C6235 l analog circuit characteristics and current consumption E0C6235 (normal mode) * 1: * 2: the relationships among v b0 ? b7 are v b0 >v b1 >v b2 >...v b5 >v b6 >v b7 . the bld circuit, sub-bld circuit and analog comparator are in the off status. unit v v v v v v v v v v v s v s v mv ms a a (unless otherwise specified: v dd =0v, v ss =-3.0v, f osc1 =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 ? l3 are internal voltage , c1?6=0.1 f) max. -0.95 2? l1 0.9 3? l1 0.9 -2.05 -2.10 -2.15 -2.20 -2.25 -2.30 -2.35 -2.40 100 -2.25 100 v dd -0.9 10 3 4.0 10.0 typ. -1.05 -2.20 -2.25 -2.30 -2.35 -2.40 -2.45 -2.50 -2.55 -2.40 1.8 6.0 min. -1.15 2? l1 -0.1 3? l1 -0.1 -2.35 -2.40 -2.45 -2.50 -2.55 -2.60 -2.65 -2.70 -2.55 v ss +0.3 characteristic internal voltage bld voltage * 1 bld circuit response time sub-bld voltage sub-bld circuit response time analog comparator input voltage analog comparator offset voltage analog comparator response time current consumption symbol v l1 v l2 v l3 v b0 v b1 v b2 v b3 v b4 v b5 v b6 v b7 t b v bs t bs v ip v im v of t amp i op condition connect 1m w load resistor between v dd and v l1 (without panel load) connect 1m w load resistor between v dd and v l2 (without panel load) connect 1m w load resistor between v dd and v l3 (without panel load) blc="0" blc="1" blc="2" blc="3" blc="4" blc="5" blc="6" blc="7" noninverted input (ampp) inverted input (ampm) v ip =-1.5v, v im =v ip 15mv during halt during operation * 2 without panel load E0C6235 (heavy load protection mode) * 1: * 2: the relationships among v b0 ? b7 are v b0 >v b1 >v b2 >...v b5 >v b6 >v b7 . the bld circuit and sub-bld circuit are in the on status (hlmod="1", bls="0"). the analog comparator is in the off status. unit v v v v v v v v v v v s v s v mv ms a a (unless otherwise specified: v dd =0v, v ss =-3.0v, f osc1 =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 ? l3 are internal voltage , c1?6=0.1 f) max. -0.95 2? l1 0.9 3? l1 0.9 -2.05 -2.10 -2.15 -2.20 -2.25 -2.30 -2.35 -2.40 100 -2.25 100 v dd -0.9 10 3 90 100 typ. -1.05 -2.20 -2.25 -2.30 -2.35 -2.40 -2.45 -2.50 -2.55 -2.40 35 40 min. -1.15 2? l1 -0.1 3? l1 -0.1 -2.35 -2.40 -2.45 -2.50 -2.55 -2.60 -2.65 -2.70 -2.55 v ss +0.3 characteristic internal voltage bld voltage * 1 bld circuit response time sub-bld voltage sub-bld circuit response time analog comparator input voltage analog comparator offset voltage analog comparator response time current consumption symbol v l1 v l2 v l3 v b0 v b1 v b2 v b3 v b4 v b5 v b6 v b7 t b v bs t bs v ip v im v of t amp i op condition connect 1m w load resistor between v dd and v l1 (without panel load) connect 1m w load resistor between v dd and v l2 (without panel load) connect 1m w load resistor between v dd and v l3 (without panel load) blc="0" blc="1" blc="2" blc="3" blc="4" blc="5" blc="6" blc="7" noninverted input (ampp) inverted input (ampm) v ip =-1.5v, v im =v ip 15mv during halt during operation * 2 without panel load
7 E0C6235 e0c62l35 (normal mode) * 1: * 2: the relationships among v b0 ? b7 are v b0 >v b1 >v b2 >...v b5 >v b6 >v b7 . the bld circuit, sub-bld circuit and analog comparator are in the off status. unit v v v v v v v v v v v s v s v mv ms a a (unless otherwise specified: v dd =0v, v ss =-1.5v, f osc1 =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 ? l3 are internal voltage , c1?6=0.1 f) max. -0.95 2? l1 0.9 3? l1 0.9 -0.95 -1.00 -1.05 -1.10 -1.15 -1.20 -1.25 -1.30 100 -1.10 100 v dd -0.9 20 3 3.0 8.0 typ. -1.05 -1.05 -1.10 -1.15 -1.20 -1.25 -1.30 -1.35 -1.40 -1.20 1.5 5.0 min. -1.15 2? l1 -0.1 3? l1 -0.1 -1.15 -1.20 -1.25 -1.30 -1.35 -1.40 -1.45 -1.50 -1.30 v ss +0.3 characteristic internal voltage bld voltage * 1 bld circuit response time sub-bld voltage sub-bld circuit response time analog comparator input voltage analog comparator offset voltage analog comparator response time current consumption symbol v l1 v l2 v l3 v b0 v b1 v b2 v b3 v b4 v b5 v b6 v b7 t b v bs t bs v ip v im v of t amp i op condition connect 1m w load resistor between v dd and v l1 (without panel load) connect 1m w load resistor between v dd and v l2 (without panel load) connect 1m w load resistor between v dd and v l3 (without panel load) blc="0" blc="1" blc="2" blc="3" blc="4" blc="5" blc="6" blc="7" noninverted input (ampp) inverted input (ampm) v ip =-1.1v, v im =v ip 30mv during halt during operation * 2 without panel load e0c62l35 (heavy load protection mode) * 1: * 2: the relationships among v b0 ? b7 are v b0 >v b1 >v b2 >...v b5 >v b6 >v b7 . the bld circuit and sub-bld circuit are in the on status (hlmod="1", bls="0"). the analog comparator is in the off status. unit v v v v v v v v v v v s v s v mv ms a a (unless otherwise specified: v dd =0v, v ss =-1.5v, f osc1 =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 ? l3 are internal voltage , c1?6=0.1 f) max. -0.95 2? l1 0.85 3? l1 0.85 -0.95 -1.00 -1.05 -1.10 -1.15 -1.20 -1.25 -1.30 100 -1.10 100 v dd -0.9 20 3 7.0 18.0 typ. -1.05 -1.05 -1.10 -1.15 -1.20 -1.25 -1.30 -1.35 -1.40 -1.20 3.0 10.0 min. -1.15 2? l1 -0.1 3? l1 -0.1 -1.15 -1.20 -1.25 -1.30 -1.35 -1.40 -1.45 -1.50 -1.30 v ss +0.3 characteristic internal voltage bld voltage * 1 bld circuit response time sub-bld voltage sub-bld circuit response time analog comparator input voltage analog comparator offset voltage analog comparator response time current consumption symbol v l1 v l2 v l3 v b0 v b1 v b2 v b3 v b4 v b5 v b6 v b7 t b v bs t bs v ip v im v of t amp i op condition connect 1m w load resistor between v dd and v l1 (without panel load) connect 1m w load resistor between v dd and v l2 (without panel load) connect 1m w load resistor between v dd and v l3 (without panel load) blc="0" blc="1" blc="2" blc="3" blc="4" blc="5" blc="6" blc="7" noninverted input (ampp) inverted input (ampm) v ip =-1.1v, v im =v ip 30mv during halt during operation * 2 without panel load
8 E0C6235 e0c62a35 (normal mode) * 1: * 2: the relationships among v b0 ? b7 are v b0 >v b1 >v b2 >...v b5 >v b6 >v b7 . the bld circuit, sub-bld circuit and analog comparator are in the off status. unit v v v v v v v v v v v s v s v mv ms a a a (unless otherwise specified: v dd =0v, v ss =-3.0v, f osc1 =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 ? l3 are internal voltage , c1?6=0.1 f) max. -0.95 2? l1 0.9 3? l1 0.9 -2.05 -2.10 -2.15 -2.20 -2.25 -2.30 -2.35 -2.40 100 -2.25 100 v dd -0.9 10 3 5.0 15 300 typ. -1.05 -2.20 -2.25 -2.30 -2.35 -2.40 -2.45 -2.50 -2.55 -2.40 2.0 8.0 130 min. -1.15 2? l1 -0.1 3? l1 -0.1 -2.35 -2.40 -2.45 -2.50 -2.55 -2.60 -2.65 -2.70 -2.55 v ss +0.3 characteristic internal voltage bld voltage * 1 bld circuit response time sub-bld voltage sub-bld circuit response time analog comparator input voltage analog comparator offset voltage analog comparator response time current consumption symbol v l1 v l2 v l3 v b0 v b1 v b2 v b3 v b4 v b5 v b6 v b7 t b v bs t bs v ip v im v of t amp i op condition connect 1m w load resistor between v dd and v l1 (without panel load) connect 1m w load resistor between v dd and v l2 (without panel load) connect 1m w load resistor between v dd and v l3 (without panel load) blc="0" blc="1" blc="2" blc="3" blc="4" blc="5" blc="6" blc="7" noninverted input (ampp) inverted input (ampm) v ip =-1.5v, v im =v ip 15mv during halt during operation at 32khz * 2 during operation at 500khz * 2 without panel load e0c62a35 (heavy load protection mode) * 1: * 2: the relationships among v b0 ? b7 are v b0 >v b1 >v b2 >...v b5 >v b6 >v b7 . the bld circuit and sub-bld circuit are in the on status (hlmod="1", bls="0"). the analog comparator is in the off status. unit v v v v v v v v v v v s v s v mv ms a a a (unless otherwise specified: v dd =0v, v ss =-3.0v, f osc1 =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 ? l3 are internal voltage , c1?6=0.1 f) max. -0.95 2? l1 0.9 3? l1 0.9 -2.05 -2.10 -2.15 -2.20 -2.25 -2.30 -2.35 -2.40 100 -2.25 100 v dd -0.9 10 3 40 50 350 typ. -1.05 -2.20 -2.25 -2.30 -2.35 -2.40 -2.45 -2.50 -2.55 -2.40 22 28 150 min. -1.15 2? l1 -0.1 3? l1 -0.1 -2.35 -2.40 -2.45 -2.50 -2.55 -2.60 -2.65 -2.70 -2.55 v ss +0.3 characteristic internal voltage bld voltage * 1 bld circuit response time sub-bld voltage sub-bld circuit response time analog comparator input voltage analog comparator offset voltage analog comparator response time current consumption symbol v l1 v l2 v l3 v b0 v b1 v b2 v b3 v b4 v b5 v b6 v b7 t b v bs t bs v ip v im v of t amp i op condition connect 1m w load resistor between v dd and v l1 (without panel load) connect 1m w load resistor between v dd and v l2 (without panel load) connect 1m w load resistor between v dd and v l3 (without panel load) blc="0" blc="1" blc="2" blc="3" blc="4" blc="5" blc="6" blc="7" noninverted input (ampp) inverted input (ampm) v ip =-1.5v, v im =v ip 15mv during halt during operation at 32khz * 2 during operation at 500khz * 2 without panel load
9 E0C6235 l oscillation characteristics the oscillation characteristics change depending on the conditions (components used, board pattern, etc.). use the follow- ing characteristics as reference values. E0C6235 (crystal oscillation circuit) unit v v pf ppm ppm ppm v m w (unless otherwise specified: v dd =0v, v ss =-3.0v, crystal: c-002r (c i =35k w ), c g =25pf, c d =built-in, ta=25 c) max. 5 10 -3.5 typ. 20 45 min. -1.8 -1.8 -10 35 200 characteristic oscillation start voltage oscillation stop voltage built-in capacitance (drain) frequency/voltage deviation frequency/ic deviation frequency adjustment range harmonic oscillation start voltage permitted leak resistance symbol vsta vstp c d ? f/ ? v ? f/ ? ic ? f/ ? c g v hho r leak condition t sta 5sec t stp 10sec including the parasitic capacity inside the ic v ss =-1.8 to -3.5v c g =5 to 25pf between osc1 and v dd , v ss (v ss ) (v ss ) (v ss ) e0c62l35 (crystal oscillation circuit) * 1: items enclosed in parentheses ( ) are those used when operating at heavy load protection mode. unit v v pf ppm ppm ppm v m w (unless otherwise specified: v dd =0v, v ss =-1.5v, crystal: c-002r (c i =35k w ), c g =25pf, c d =built-in, ta=25 c) max. 5 10 -1.7 typ. 20 45 min. -1.1 -1.1(-0.9) * 1 -10 35 200 characteristic oscillation start voltage oscillation stop voltage built-in capacitance (drain) frequency/voltage deviation frequency/ic deviation frequency adjustment range harmonic oscillation start voltage permitted leak resistance symbol vsta vstp c d ? f/ ? v ? f/ ? ic ? f/ ? c g v hho r leak condition t sta 5sec t stp 10sec including the parasitic capacity inside the ic v ss =-1.1 to -1.7v (-0.9) * 1 c g =5 to 25pf between osc1 and v dd , v ss (v ss ) (v ss ) (v ss ) e0c62a35 (crystal oscillation circuit) unit v v pf ppm ppm ppm v m w (unless otherwise specified: v dd =0v, v ss =-3.0v, crystal: c-002r (c i =35k w ), c g =25pf, c d =built-in, ta=25 c) max. 5 10 -3.5 typ. 20 45 min. -2.2 -2.2 -10 35 200 characteristic oscillation start voltage oscillation stop voltage built-in capacitance (drain) frequency/voltage deviation frequency/ic deviation frequency adjustment range harmonic oscillation start voltage permitted leak resistance symbol vsta vstp c d ? f/ ? v ? f/ ? ic ? f/ ? c g v hho r leak condition t sta 5sec t stp 10sec including the parasitic capacity inside the ic v ss =-2.2 to -3.5v c g =5 to 25pf between osc1 and v dd , v ss (v ss ) (v ss ) (v ss ) e0c62a35 (cr oscillation circuit) unit % v ms v (unless otherwise specified: v dd =0v, v ss =-3.0v, r cr =82k w , ta=25 c) max. 30 3 typ. 480khz min. -30 -2.2 -2.2 characteristic oscillation frequency dispersion oscillation start voltage oscillation start time oscillation stop voltage symbol f osc3 vsta t sta vstp condition v ss =-2.2 to -3.5v (v ss ) (v ss ) e0c62a35 (ceramic oscillation circuit) unit v ms v (unless otherwise specified: v dd =0v, v ss =-3.0v, ceramic oscillation: 500khz, c gc =c dc =100pf, ta=25 c) max. 5 typ. min. -2.2 -2.2 characteristic oscillation start voltage oscillation start time oscillation stop voltage symbol vsta t sta vstp condition v ss =-2.2 to -3.5v (v ss ) (v ss )
10 E0C6235 ?k00 ?k03 ?k10 ?k20 ?k23 ?p00 ?p03 ?p10 ?p13 ?sin ?sclk ?sout ?ampm ?ampp ?r00 ?r03 ?cc ?cb ?ca ?v l1 ?v l2 ?v l3 ?v dd ?osc1 ?osc2 ?v s1 ?osc3 ?osc4 ?reset ?test ?v ss ?r12(fout) ?r11(lamp) ?r13 ?r10(bz) e0c 6235/62l35 ?seg0 ?seg47 ?com0 ?com3 i i/o o lamp piezo + x'tal c c 1 gx c p c 3 c 4 c 2 c 5 c 6 n.c. n.c. 1.5 v (e0c62l35) or 3.0 v (E0C6235) lcd panel normal off s i o ?k00 ?k03 ?k10 ?k20 ?k23 ?p00 ?p03 ?p10 ?p13 ?sin ?sclk ?sout ?ampm ?ampp ?r00 ?r03 ?r12(fout) ?r11(lamp) ?r13 ?r10(bz) ?seg0 ?seg47 ?com0 ?com3 i i/o o lcd panel s i o e0c62a35 lamp piezo + x'tal c c 1 3.0 v cr * 1 * 2 r cr c gc c dc gx c p c 3 c 4 c 2 c 5 c 6 * 1 ceramic oscillation * 2 cr oscillation ?cc ?cb ?ca ?v l1 ?v l2 ?v l3 ?v dd ?osc1 ?osc2 ?v s1 ?osc4 ?reset ?test ?v ss ?osc3 normal off n basic external connection diagram note: the above table is simply an example, and is not guaranteed to work. x'tal c gx cr c gc c dc r cr c1~c6 cp crystal oscillator trimmer capacitor ceramic oscillator gate capacitance drain capacitance resistance for cr oscillation 32.768khz or 38.4khz ci(max.)=35k w 5~25pf 500khz 100pf 100pf 82k w 0.1 f 3.3 f
11 E0C6235 n package dimensions plastic qfp5-100pin unit: mm plastic qfp15-100pin 20 0.1 25.6 0.4 51 80 14 0.1 19.6 0.4 31 50 index 0.3 0.1 30 1 100 81 2.7 0.1 0.26 3.4 max 2.8 1.5 0 12 0.15 0.05 0.65 14 ?.1 16 ?.4 51 75 14 ?.1 16 ?.4 26 50 index 0.18 25 1 100 76 1.4 ?.1 0.1 1.7 max 1 0.5 ?.2 0 10 0.125 0.5 +0.1 ?.05 +0.05 ?.025
E0C6235 notice: no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko ep son. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is n o representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to an y intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accord ance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade control law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. ? seiko epson corporation 1999 all right reserved. seiko epson corporation electronic devices marketing division ic marketing & engineering group ed international marketing department i (europe & u.s.a.) 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5812 fax : 042-587-5564 ed international marketing department ii (asia) 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5814 fax : 042-587-5110

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